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A29801B series 1m x 8 bit / 512k x 16 bit cmos 5.0 volt-only, preliminary boot sector flash memory preliminary (june, 2016, version 0.0) amic technology, corp. amic reserves the right to change products and specifications discussed herein without notice. document title 1m x 8 bit / 512k x 16 bit cmos 5.0 vo lt-only, boot sector flash memory revision history rev. no. history issue date remark 0.0 initial issue june 16, 2016 preliminary
A29801B series 1m x 8 bit / 512k x 16 bit cmos 5.0 volt-only, preliminary boot sector flash memory preliminary (june, 2016, version 0.0) 1 amic technology, corp. features ? single power supply operation - full voltage range: 4.5 to 5.5 volt for read and write operations ? access time: - 55ns (max.) ? current: - 20ma typical active read current - 30ma typical program/erase current - 6ua typical cmos standby ? flexible sector architecture - 16 kbyte/ 8 kbytex2/ 32 kb yte/ 64 kbytex15 sectors - 8 kword/ 4 kwordx2/ 16 kword/ 32 kwordx15 sectors - any combination of sectors can be erased - supports full chip erase - sector protection: a hardware method of protecting sectors to prevent any inadvertent program or eras e operations within that sector. temporary sector unpr otect feature allows code changes in previously locked sectors ? industrial operating temperatur e range: -40oc to +85oc for -u series ? unlock bypass program command - reduces overall programming time when issuing multiple program command sequence ? top or bottom boot block configurations available ? embedded algorithms - embedded erase algorithm will automatically erase the entire chip or any combinatio n of designated sectors and verify the erased sectors - embedded program algorithm automatically writes and verifies data at specified addresses ? minimum 100,000 program/erase cycles per sector ? 20-year data retention at 125oc - reliable operation for the life of the system ? compatible with jedec-standards - pinout and software compatible with single-power-supply flash memory standard - superior inadvertent write protection ? data polling and toggle bits - provides a software method of detecting completion of program or erase operations ? ready / busy pin (ry / by ) - provides a hardware method of detecting completion of program or erase operations ? erase suspend/erase resume - suspends a sector erase operation to read data from, or program data to, a non-erasing sector, then resumes the erase operation ? hardware reset pin ( reset ) - hardware method to reset the device to reading array data ? package options - 48-pin tsop (i) or 48-ball tfbga - all pb-free (lead-free) pr oducts are rohs2.0 compliant general description the A29801B is an 8mbit, 5.0 volt-only flash memory organized as 1,048,576 bytes of 8 bits or 524,288 words of 16 bits each. the 8 bits of data appear on i/o 0 - i/o 7 ; the 16 bits of data appear on i/o 0 ~i/o 15 . the is offered in 48-ball fbga and 48-pin tsop packages. this device is designed to be programmed in-system wi th the standard system 5.0 volt vcc supply. additional 12. 0 volt vpp is not required for in-system write or erase operations. however, the A29801B can also be programmed in standard eprom programmers. the A29801B has the first toggle bit, i/o 6 , which indicates whether an embedded program or erase is in progress, or it is in the erase suspend. besides the i/o 6 toggle bit, the A29801B has a second toggle bit, i/o 2 , to indicate whether the addressed sector is being selected for erase. the A29801B also offers the ability to program in the erase suspend mode. the standard A29801B offers access time of 55ns, allowing high-speed microprocessors to operate without wait states. to elim inate bus contention the device has separate chip enable ( ce ), write enable ( we ) and output enable ( oe ) controls. the device requires only a single 5.0 volt power supply for both read and write functions. internally generated and regulated voltages are provid ed for the program and erase operations. the A29801B is entirely software command set compatible with the jedec single-power-supply flash standard. commands are written to the command register using standard microprocessor write ti mings. register contents serve as input to an internal st ate-machine that controls the erase and programming circuitry. write cycles also internally latch addresses and data needed for the programming and erase operations. reading data out of the device is similar to reading from other flash or eprom devices. device programming occurs by writing the proper program command sequence. this initiates the embedded program algorithm - an internal algorithm that automatically times the program pulse widths and verifies proper program margin. device erasure occurs by executing the proper erase command sequence. this initiates the embedded erase algorithm - an internal algor ithm that automatically preprograms the array (if it is not already programmed)
A29801B series preliminary (june, 2016, version 0.0) 2 amic technology, corp. before executing the erase oper ation. during erase, the device automatically times the erase pulse widths and verifies proper erase margin. the unlock bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. the host system can detect w hether a program or erase operation is complete by observing the ry / by pin, or by reading the i/o 7 ( data polling) and i/o 6 (toggle) status bits. after a program or erase cycle has been completed, the device is ready to read array data or accept another command. the sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. the A29801B is fully erased when shipped from the factory. the hardware sector protection feature disables operations for both program and erase in any combination of the sectors of memory. this can be achieved via programming equipment. the erase suspend/erase resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any other se ctor that is not selected for erasure. true background eras e can thus be achieved. the hardware reset pin terminates any operation in progress and resets the internal state machine to reading array data. the reset pin may be tied to the system reset circuitry. a system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the flash memory. the device offers power-savi ng features. the system can place the device into the st andby mode. power consumption is greatly reduced in standby mode. pin configurations ? tsop (i) A29801Bv 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a14 a13 a12 a11 a10 a9 a8 nc we reset nc nc ry/by a18 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 i/o 2 i/o 10 i/o 3 i/o 11 vcc i/o 4 i/o 12 i/o 5 i/o 13 i/o 6 i/o 14 i/o 7 i/o 15(a-1 ) vss byte a16 a15 nc 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 i/o 9 i/o 1 i/o 8 i/o 0 oe vss ce a0 a17 a7 a6 a5 a4 a3 a2 a1
A29801B series preliminary (june, 2016, version 0.0) 3 amic technology, corp. pin configurations (continued) a6 b6 c6 d6 e6 f6 g6 h6 tfbga top view, balls facing down a5 b5 c5 d5 e5 f5 g5 h5 a4 b4 c4 d4 e4 f4 g4 h4 a3 b3 c3 d3 e3 f3 g3 h3 a2 b2 c2 d2 e2 f2 g2 h2 a1 b1 c1 d1 e1 f1 g1 h1 a13a12a14a15a16 byte i/o 15 (a-1) vss a9 a8 a10 a11 i/o 7 i/o 14 i/o 13 i/o 6 we reset nc nc i/o 5 i/o 12 vcc i/o 4 ry/by nc a18 nc i/o 2 i/o 10 i/o 11 i/o 3 a7 a17 a6 a5 i/o 0 i/o 8 i/o 9 i/o 1 a3 a4 a2 a1 a0 ce oe vss
A29801B series preliminary (june, 2016, version 0.0) 4 amic technology, corp. block diagram pin descriptions pin no. description a0 - a18 address inputs i/o 0 - i/o 14 data inputs/outputs i/o 15 data input/out put, word mode i/o 15 (a -1 ) a -1 lsb address input, byte mode ce chip enable we write enable oe output enable reset hardware reset byte selects byte mode or word mode ry/ by ready/ busy - output vss ground vcc power supply nc pin not connected internally state control command register address latch x-decoder y-decoder chip enable output enable logic cell matrix y-gating vcc detector pgm voltage generator data latch input/output buffers erase voltage generator vcc vss we ce oe a0-a18 i/o 0 - i/o 15 (a-1) timer stb stb reset sector switches byte ry/by
A29801B series preliminary (june, 2016, version 0.0) 5 amic technology, corp. absolute maximum ratings* storage temperature plastic packages ?... -65 c to +150 c ambient temperature with power applied... -55 c to +125 c voltage with respect to ground vcc (note 1) ?????????????? -2.0v to +6.5v a9, oe & reset (note 2) ??????? -2.0v to +11.5v all other pins (note 1) ?????.?????. -2.0v to 6.5v output short circuit current (note 3) ??????.. 200ma notes: 1. minimum dc voltage on input or i/o pins is -0.5v. during voltage transitions, input or i/o pins may undershoot vss to -2.0v for periods of up to 20ns. maximum dc voltage on input and i/o pins is vcc +0.5v. during voltage transitions, input or i/o pins may overshoot to vcc +1.5v for periods up to 20ns. 2. minimum dc input voltage on a9, oe and reset is - 0.5v. during voltage transitions, a9, oe and reset may overshoot vss to -2.0v for periods of up to 20ns. maximum dc input voltage on a9 is +11.5v which may overshoot to 12.5v for periods up to 20ns. 3. no more than one output is s horted at a time. duration of the short circuit should not be greater than one second. *comments stresses above those listed under "absolute maximum ratings" may cause permanent damage to this device. these are stress ratings only. functional operation of this device at these or any other conditions above those indicated in the oper ational sections of these specification is not implie d or intended. exposure to the absolute maximum rating conditions for extended periods may affect device reliability. operating ranges commercial devices ambient temperature (t a ) ????????? 0 c to +70 c extended range devices ambient temperature (t a ) ???????? -40 c to +85 c vcc supply voltages vcc for all devices ??????????? +4.5v to +5.5v operating ranges define t hose limits between which the functionally of the device is guaranteed. device bus operations this section describes the requirements and use of the device bus operations, which are initiated through the internal command register. the command register itself does not occupy any addressable memory location. the register is composed of latches that st ore the commands, along with the address and data information needed to execute the command. the contents of the register serve as inputs to the internal state machine. the st ate machine outputs dictate the function of the device. the appr opriate device bus operations table lists the inputs and control levels required, and the resulting output. the following subsections describe each of these operations in further detail. table 1. A29801B device bus operations i/o 8 - i/o 15 operation ce oe we reset a0 ? a18 (note 1) i/o 0 - i/o 7 byte =v ih byte =v il read l l h h a in d out d out i/o 8 ~i/o 14 =high-z i/o 15 =a -1 write l h l h a in d in d in i/o 8 ~i/o 14 =high-z i/o 15 =a -1 cmos standby vcc 0.3 v x x vcc 0.3 v x high-z high-z high-z output disable l h h h x high-z high-z high-z hardware reset x x x l x high-z high-z high-z sector protect (see note 2) l h l v id sector address, a6=l, a1=h, a0=l d in x x sector unprotect (see note 2) l h l v id sector address, a6=h, a1=h, a0=l d in x x temporary sector unprotect x x x v id a in d in d in x legend: l = logic low = v il , h = logic high = v ih , v id = 10.5 1.0v, x = don't care, d in = data in, d out = data out, a in = address in notes: 1. addresses are a18:a0 in word mode ( byte =v ih ), a18: a -1 in byte mode ( byte =v il ). 2. see the ?sector protection/unprot ection? section and temporary sector unprotect for more information.
A29801B series preliminary (june, 2016, version 0.0) 6 amic technology, corp. word/byte configuration the byte pin determines whether the i/o pins i/o 15 -i/o 0 operate in the byte or word configuration. if the byte pin is set at logic ?1?, the device is in word configuration, i/o 15 -i/o 0 are active and controlled by ce and oe . if the byte pin is set at logic ?0?, the device is in byte configuration, and only i/o 0 -i/o 7 are active and controlled by ce and oe . i/o 8 -i/o 14 are tri-stated, and i/o 15 pin is used as an input for the lsb(a-1) address function. requirements for reading array data to read array data from the out puts, the system must drive the ce and oe pins to v il . ce is the power control and selects the device. oe is the output cont rol and gates array data to the output pins. we should remain at v ih all the time during read operation. the byte pin determines whether the device outputs array data in words and bytes. the internal state machine is set for reading array data upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the memory content occurs during the power transition. no command is necessary in this mode to obtain array data. standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the devi ce data outputs. the device remains enabled for read access until the command register contents are altered. see "reading array data" for more information. refer to the ac read operations table for ti ming specifications and to the read operations timings diagram for the timing waveforms, l cc1 in the dc characteristics table represents the active current specification for reading array data. writing commands/command sequences to write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive we and ce to v il , and oe to v ih . for program operations, the byte pin determines whether the device accepts program data in bytes or words, refer to ?word/byte configuration? for more information. the device features an unlock bypass mode to facilitate faster programming. once the device enters the unlock bypass mode, only two write cycles are required to program a word or byte, instead of four. the ?word/byte program command sequence? and ?unlock bypass command sequence? has detail descriptions on programming data to the device using both standard and unlock bypass command sequence. an erase operation can erase one sector, multiple sect ors, or the ent ire device. the sector address tables indicate the address range that each sector occupies. a "sector address" consists of the address inputs required to uniquely select a sector. see the "command definitions" section for details on erasing a sector or the entire chip, or sus pending/resuming the erase operation. after the system writes the autoselect command sequence, the device enters the autoselec t mode. the system can then read autoselect codes from the in ternal register (which is separate from the memory array) on i/o 7 - i/o 0 . standard read cycle timings apply in this mode. refer to the "autoselect mode" and "autoselect command sequence" sections for mo re information. i cc2 in the dc characteristics table represents the active current specification for the write mode. the "ac characteristics" section contai ns timing specification tables and timing diagrams for write operations. program and erase operation status during an erase or program operation, the system may check the status of the operation by readin g the status bits on i/o 7 - i/o 0 . standard read cycle timings and i cc read specifications apply. refer to "write operation status" for more information, and to each ac characteristics section for timing diagrams. standby mode when the system is not reading or writing to the device, it can place the device in the standby mode. in this mode, current consumption is greatl y reduced, and the outputs are placed in the high impedanc e state, indepen dent of the oe input. the device enters the cmos standby mode when the ce & reset pins are both held at vcc 0.5v. (note that this is a more restricted voltage range than v ih .) if ce and reset are held at v ih , but not within vcc 0.5v, the device will be in the standby mode, but the st andby current will be greater. the device requires the standard access time (t ce ) before it is ready to read data. if the device is deselected during erasure or programming, the device draws active curr ent until the operation is completed. i cc3 and i cc4 in the dc characteristics tables represent the standby current specification. output disable mode when the oe input is at v ih , output from the device is disabled. the output pins are placed in the high impedance state. reset : hardware reset pin the reset pin provides a hardware method of resetting the device to reading array data. when the system drives the reset pin low for at least a period of t rp , the device immediately terminates any operat ion in progress, tristates all data output pins, and ignores all read/write attempts for the duration of the reset pulse. the device also resets the internal state machine to reading array data. the operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. current is reduced fo r the duration of the reset pulse. when reset is held at vss 0.5v, the device draws cmos standby current (i cc4 ). if reset is held at v il but not within vss 0.5v, the standby current will be greater. the reset pin may be tied to the system reset circuitry. a system reset would thus also reset the flash memory, enabling the system to read the boot-up firmware from the flash memory. if reset is asserted during a progr am or erase operation, the ry/ by pin remains a ?0? (busy) until the internal reset operation is complete, which requires a time t ready (during embedded algorithms). the sy stem can thus monitor ry/ by to determine whether the reset operation is complete. if reset is asserted when a program or erase
A29801B series preliminary (june, 2016, version 0.0) 7 amic technology, corp. operation is not executing (ry/ by pin is ?1?), the reset operation is completed within a time of t ready (not during embedded algorithms). the system can read data t rh after the reset pin return to v ih . refer to the ac characteristics tables for reset parameters and diagram. table 2. A29801B top boot block sector address table address range (in hexadecimal) sector a18 a17 a16 a15 a14 a13 a12 sector size (kbytes/ kwords) byte mode (x8) word mode (x16) sa0 0 0 0 0 x x x 64/32 000000h - 00ffffh 00000h - 07fffh sa1 0 0 0 1 x x x 64/32 010000h - 01ffffh 08000h - 0ffffh sa2 0 0 1 0 x x x 64/32 020000h - 02ffffh 10000h - 17fffh sa3 0 0 1 1 x x x 64/32 030000h - 03ffffh 18000h - 1ffffh sa4 0 1 0 0 x x x 64/32 040000h - 04ffffh 20000h - 27fffh sa5 0 1 0 1 x x x 64/32 050000h - 05ffffh 28000h - 2ffffh sa6 0 1 1 0 x x x 64/32 060000h - 06ffffh 30000h - 37fffh sa7 0 1 1 1 x x x 64/32 070000h - 07ffffh 38000h - 3ffffh sa8 1 0 0 0 x x x 64/32 080000h - 08ffffh 40000h - 47fffh sa9 1 0 0 1 x x x 64/32 090000h - 09ffffh 48000h - 4ffffh sa10 1 0 1 0 x x x 64/32 0a0000h - 0affffh 50000h - 57fffh sa11 1 0 1 1 x x x 64/32 0b0000h - 0bffffh 58000h - 5ffffh sa12 1 1 0 0 x x x 64/32 0c00 00h - 0cffffh 60000h - 67fffh sa13 1 1 0 1 x x x 64/32 0d00 00h - 0dffffh 68000h - 6ffffh sa14 1 1 1 0 x x x 64/32 0e0000h - 0effffh 70000h - 77fffh sa15 1 1 1 1 0 x x 32/16 0f000 0h - 0f7fffh 78000h - 7bfffh sa16 1 1 1 1 1 0 0 8/4 0f8000h - 0f9fffh 7c000h - 7cfffh sa17 1 1 1 1 1 0 1 8/4 0fa000h - 0fbfffh 7d000h - 7dfffh sa18 1 1 1 1 1 1 x 16/8 0fc000h - 0fffffh 7e000h - 7ffffh note: address range is a18 : a -1 in byte mode and a18 : a0 in word mode. see ?word/byte configuration? section.
A29801B series preliminary (june, 2016, version 0.0) 8 amic technology, corp. table 3. A29801B bottom boot block sector address table address range (in hexadecimal) sector a18 a17 a16 a15 a14 a13 a12 sector size (kbytes/ kwords) byte mode (x8) word mode (x16) sa0 0 0 0 0 0 0 x 16/8 000 000h - 003fffh 00000h - 01fffh sa1 0 0 0 0 0 1 0 8/4 004 000h - 005fffh 02000h - 02fffh sa2 0 0 0 0 0 1 1 8/4 006 000h - 007fffh 03000h - 03fffh sa3 0 0 0 0 1 x x 32/16 008000h - 00ffffh 04000h - 07fffh sa4 0 0 0 1 x x x 64/32 010000h - 01ffffh 08000h - 0ffffh sa5 0 0 1 0 x x x 64/32 020000h - 02ffffh 10000h - 17fffh sa6 0 0 1 1 x x x 64/32 030000h - 03ffffh 18000h - 1ffffh sa7 0 1 0 0 x x x 64/32 040000h - 04ffffh 20000h - 27fffh sa8 0 1 0 1 x x x 64/32 050000h - 05ffffh 28000h - 2ffffh sa9 0 1 1 0 x x x 64/32 060000h - 06ffffh 30000h - 37fffh sa10 0 1 1 1 x x x 64/32 070000h - 07ffffh 38000h - 3ffffh sa11 1 0 0 0 x x x 64/32 080000h - 08ffffh 40000h - 47fffh sa12 1 0 0 1 x x x 64/32 090000h - 09ffffh 48000h - 4ffffh sa13 1 0 1 0 x x x 64/32 0a0000h - 0affffh 50000h - 57fffh sa14 1 0 1 1 x x x 64/32 0b0000h - 0bffffh 58000h - 5ffffh sa15 1 1 0 0 x x x 64/32 0c00 00h - 0cffffh 60000h - 67fffh sa16 1 1 0 1 x x x 64/32 0d00 00h - 0dffffh 68000h - 6ffffh sa17 1 1 1 0 x x x 64/32 0e0000h - 0effffh 70000h - 77fffh sa18 1 1 1 1 x x x 64/32 0f 0000h - 0fffffh 78000h - 7ffffh note: address range is a18 : a -1 in byte mode and a18 : a0 in word mode. see ?word/byte configuration? section.
A29801B series preliminary (june, 2016, version 0.0) 9 amic technology, corp. autoselect mode the autoselect mode provides manufacturer and device identification, and sector prot ection verification, through identifier codes output on i/o 7 - i/o 0 . this mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. however, the autoselect codes can also be accessed in-system through the command register. when using programming equipment, the autoselect mode requires v id (9.5v to 11.5 v) on address pin a9. address pins a6, a1, and a0 must be as shown in autoselect codes (high voltage method) table. in addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits. refer to the corresponding sector address tables. the command definitions table shows the remaining address bits that are don't care. when all necessary bits have been set as required, the programming equi pment may then read the corresponding identifier code on i/o 7 - i/o 0 .to access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in the command definitions table. this method does not require v id . see "command definitions" for details on using the autoselect mode. table 4. A29801B autoselect codes (high voltage method) description mode ce oe we a18 to a12 a11 to a10 a9 a8 to a7 a6 a5 to a2 a1 a0 i/o 8 to i/o 15 i/o 7 to i/o 0 manufacturer id: amic l l h x x v id x l x l l x 37h word 22h d6h device id: A29801B (top boot block) byte l l h x x v id xlxlh x d6h word 22h 58h device id: A29801B (bottom boot block) byte l l h x x v id xlxlh x 58h continuation id l l h x x v id x l x h h x 7fh x 01h (protected) sector protection verification l l h sa x v id xlxhl x 00h (unprotected) l=logic low= v il , h=logic high=v ih , sa=sector address, x=don?t care. note: the autoselect codes may also be accessed in-system via command sequences.
A29801B series preliminary (june, 2016, version 0.0) 10 amic technology, corp. sector protection/unprotection the hardware sector protec tion feature disables both program and erase operations in any sector. the hardware sector unprotection feature re-enables both program and erase operations in previ ously protected sectors. it is possible to determine whether a sector is protected or unprotected. see ?autoselect mode? for details. sector protection / unprotecti on can be implemented via two methods. the primary method requires v id on the reset pin only, and can be implemented either in-system or via programming equipment. figure 2 shows the algorithm and the sector protect / unprotect timing diagram illustrates the timing waveforms for this feature. this method uses standard microprocessor bus cycle timing. for sector unprotect, all unprotected sectors must first be protected prior to the first sector unprotect write cycle. the alternate method must be implemented using programmi ng equipment. the procedure requires a high voltage (v id ) on address pin a9 and the control pins. the device is shipped with all sectors unprotected. it is possible to determine whether a sector is protected or unprotected. see "autoselect mode" for details. hardware data protection the requirement of command unlocking sequence for programming or erasing provi des data protection against inadvertent writes (refer to the command definitions table). in addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during v cc power-up transitions, or from system noise. the device is powered up to read array data to avoid accidentally writing data to the array. low vcc write inhibit when vcc is lower than v lko , the device does not accept any write cycles. this protects data during vcc power up and power down. the command register and all internal program/erase circuits are disabled, and the device resets. subsequent writes are ignor ed until vcc is greater than v lko . the system must provide the proper signals to the control pins to prevent unint entional writes when vcc is greater than v lko . write pulse "glitch" protection noise pulses of less than 5ns (typical) on oe , ce or we do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe =v il , ce = v ih or we = v ih . to initiate a write cycle, ce and we must be a logical zero while oe is a logical one. power-up write inhibit if we = ce = v il and oe = v ih during power up, the device does not accept commands on the rising edge of we . the internal state machine is automatically reset to reading array data on the initial power-up. temporary sector unprotect this feature allows temporar y unprotection of previous protected sectors to change data in-system. the sector unprotect mode is activated by setting the reset pin to v id . during this mode, formerly protected sectors can be programmed or erased by select ing the sector addresses. once v id is removed from the reset pin, all the previously protected sectors are protect ed again. figure 1 shows the algorithm, and the temporary sector unprotect diagram shows the timing waveforms, for this feature. start reset = v id (note 1) perform erase or program operations reset = v ih temporary sector unprotect completed (note 2) notes: 1. all protected sectors unprotected. 2. all previously protected sectors are protected once again. figure 1. temporary sector unprotect operation
A29801B series preliminary (june, 2016, version 0.0) 11 amic technology, corp. start plscnt=1 reset=v id wait 1 us first write cycle=60h? set up sector address sector protec: write 60h to sector address with a6=0, a1=1, a0=0 wait 150 us verify sector protect: write 40h to sector address with a6=0, a1=1, a0=0 read from sector address with a6=0, a1=1, a0=0 data=01h? protect another sector? remove v id from reset write reset command sector protect complete sector protect algorithm temporary sector unprotect mode increment plscnt plscnt =25? device failed no no no yes reset plscnt=1 yes yes no protect all sectors: the indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address start plscnt=1 reset=v id wait 1 us first write cycle=60h? no temporary sector unprotect mode yes no all sectors protected? set up first sector address sector unprotect: write 60h to sector address with a6=1, a1=1, a0=0 wait 15 ms verify sector unprotect : write 40h to sector address with a6=1, a1=1, a0=0 read from sector address with a6=1, a1=1, a0=0 data=00h? last sector verified? remove v id from reset write reset command sector unprotect complete yes yes set up next sector address no yes yes sector unprotect algorithm increment plscnt plscnt= 1000? device failed yes no no figure 2. in-system sector protect/unprotect algorithms
A29801B series preliminary (june, 2016, version 0.0) 12 amic technology, corp. command definitions writing specific address and data commands or sequences into the command register initiates device operations. the command definitions table defines the valid register command sequences. writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. all addresses are latched on the falling edge of we or ce , whichever happens later. all data is latched on the rising edge of we or ce , whichever happens first. refer to the appropriate timing diagrams in the "ac characteristics" section. reading array data the device is automatically set to reading array data after device power-up. no commands are required to retrieve data. the device is also ready to read array data after completing an embedded program or embedded erase algorithm. after the device accepts an erase suspend command, the device enters the erase suspend mode. the system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. after completing a programming operation in the erase suspend mode, the system may once again read array data with the same exception. see "erase suspend/erase resume commands" for more information on this mode. the system must issue the reset command to re-enable the device for reading array data if i/o 5 goes high, or while in the autoselect mode. see the "reset command" section, next. see also "requirements for reading array data" in the "device bus operations" section for more information. the read operations table provi des the read parameters, and read operation timings diagram shows the timing diagram. reset command writing the reset command to t he device resets the device to reading array data. address bits are don't care for this command. the reset command may be written between the sequence cycles in an erase command sequence before erasing begins. this resets the device to reading array data. once erasure begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in a program command sequence before programming begins. this resets the device to reading array data (also applies to programming in erase suspend mode). once programming begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in an autoselect command sequence. once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during erase suspend). if i/o 5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during erase suspend). autoselect command sequence the autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. the command definitions table shows the address and data requirements. this method is an alternative to that shown in the autoselect codes (high voltage method) table, which is intended for prom programmers and requires v id on address bit a9. the autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. the device then enters the autoselec t mode, and the system may read at any address any number of times, without initiating another command sequence. a read cycle at address xx00h retrieves the manufacturer code and another read cycle at xx11h retrieves the continuation code. a read cycle at address xx01h returns the device code. a read cycle containing a sector address (sa) and the address 02h in returns 01h if that sector is protected, or 00h if it is unprotected. refer to the sector address tables for valid sector addresses. the system must write the reset command to exit the autoselect mode and return to reading array data. word/byte program command sequence the system may program the device by word or byte, depending on the state of the byte pin. programming is a four-bus-cycle operation. t he program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. the program address and data are written next, which in turn initiate the embedded program algorithm. the system is not required to provide further controls or timings. the dev ice automatically provides internally generated program pulses and verify the programmed cell margin. table 5 shows the address and data requirements for the byte program command sequence. when the embedded program algorithm is complete, the device then returns to reading array data and addresses are longer latched. the system c an determine the st atus of the program operation by using i/o 7 , i/o 6 , or ry/ by . see ?white operation status? for informa tion on these status bits. any commands written to the device during the embedded program algorithm are ignored. note that a hardware reset immediately terminates the progr amming operation. the byte program command sequence should be reinitiated once the device has reset to reading array data, to ensure data integrity. programming is allowed in any sequence and across sector boundaries. a bit cannot be programmed from a ?0? back to a ?1?. attempting to do so may hal t the operat ion and set i/o5 to ?1?, or cause the data polling algorithm to indicate the operation was successful. howe ver, a succeeding read will show that the data is still ?0 ?. only erase operations can convert a ?0? to a ?1?.
A29801B series preliminary (june, 2016, version 0.0) 13 amic technology, corp. start write program command sequence data poll from system verify data ? last address ? programming completed no yes yes increment address embedded program algorithm in progress note : see the appropriate command definitions table for program command sequence. figure 3. program operation no unlock bypass command sequence the unlock bypass feature allows the system to program bytes or words to the device faster than using the standard program command sequence. the unlock bypass command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the unlock bypass command, 20h. the device then enters the unlock bypass mode. a two-cycle unlock bypass program command sequence is all that is required to program in this mode. the first cycle in this sequence contains the unlock bypass program command, a0h; the second cycle contains the program address and data. additi onal data is programmed in the same manner. this mode di spenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. table 5 shows the requirements for the command sequence. during the unlock bypass mode, only the unlock bypass program and unlock bypass reset commands are valid. to exit the unlock bypass mode, t he system must issue the two- cycle unlock bypass reset command sequence. the first cycle must contain the data 90h; the second cycle the data 00h. addresses are don?t care for both cycle. the device returns to reading array data. figure 3 illustrates the algorithm for the program operation. see the erase/program operations in ?ac characteristics? for parameters, and to program operation timings for timing diagrams. chip erase command sequence chip erase is a six-bus-cycle operation. the chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the embedded erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. the command definitions table shows the address and data requirements for the chip erase command sequence. any commands written to the chip during the embedded erase algorithm are ignored. the system can determine the status of the erase operation by using i/o 7 , i/o 6 , or i/o 2 . see "write operation status" for in formation on these status bits. when the embedded erase algorit hm is complete, the device returns to reading array data and addresses are no longer latched. figure 4 illustrates the algorith m for the erase operation. see the erase/program operations t ables in "ac characteristics" for parameters, and to the ch ip/sector erase operation timings for timing waveforms. sector erase command sequence sector erase is a six-bus-cycle operation. the sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. the command definitions table shows the address and data requirements for the sector erase command sequence. the device does not require t he system to preprogram the memory prior to erase. the embedded erase algorithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. after the command sequence is wr itten, a sector erase time- out of 50 s begins. during the time-out period, additional sector addresses and sector erase commands may be written. loading the sector erase buffer may be done in any sequence, and the number of se ctors may be from one sector to all sectors. the time between these additional cycles must be less than 50 s, otherwise the last address and command might not be accepted, and erasure may begin. it is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. the interrupts can be re-enabled after the last sector erase command is written. if the time between additional sector erase commands can be assumed to be less than 50 s, the system need not monitor i/o 3 . any command other than sector erase or erase suspend during the time-out period resets the device to reading array data. the system must rewrite the command sequence and any additional sector addresses and commands.
A29801B series preliminary (june, 2016, version 0.0) 14 amic technology, corp. start write erase command sequence data poll from system data = ffh ? erasure completed yes embedded erase algorithm in progress note : 1. see the appropriate command definitions table for erase command sequences. 2. see "i/o 3 : sector erase timer" for more information. no figure 4. erase operation the system can monitor i/o 3 to determine if the sector erase timer has timed out. (see the " i/o 3 : sector erase timer" section.) the time-out begins fr om the rising edge of the final we pulse in the command sequence. once the sector erase operation has begun, only the erase suspend command is valid. all other commands are ignored. when the embedded erase algorit hm is complete, the device returns to reading array data and addresses are no longer latched. the system can dete rmine the status of the erase operation by using i/o 7 , i/o 6 , or i/o 2 . refer to "write operation status" for informati on on these status bits. figure 4 illustrates the algorith m for the erase operation. refer to the erase/program o perations tables in the "ac characteristics" section for parameters, and to the sector erase operations timing diagram for timing waveforms. erase suspend/erase resume commands the erase suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. this command is valid only during the sector erase operation, including the 50 s time-out period duri ng the sector erase command sequence. the erase suspend command is ignored if written during the chip erase operation or embedded program algorithm. writing the erase suspend command during the sector er ase time-out immediately terminates the time-out period and suspends the erase operation. addresses are "don't cares" when writing the erase suspend command. when the erase suspend command is written during a sector erase operation, the device requires a maximum of 20 s to suspend the erase operation. however, when the erase suspend command is wri tten during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. after the erase operation ha s been suspended, the system can read array data from or program data to any sector not selected for erasure. (the device "erase suspends" all sectors selected for erasure.) normal read and write timings and command definitions apply. reading at any address within erase-suspended sector s produces status data on i/o 7 - i/o 0 . the system can use i/o 7 , or i/o 6 and i/o 2 together, to determine if a sector is ac tively erasing or is erase- suspended. see "write operat ion status" for information on these status bits. after an erase-suspended program operation is complete, the system can once again read array data within non- suspended sectors. the system can determine the status of the program operation using the i/o 7 or i/o 6 status bits, just as in the standard program o peration. see "write operation status" for more information. the system may also write the autoselect command sequence when the device is in the erase suspend mode. the device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. when the device exits the autoselect mode, the device re verts to the erase suspend mode, and is ready for anot her valid operation. see "autoselect command sequence" for more information. the system must write the erase resume command (address bits are "don't care") to exit the erase suspend mode and continue the sector er ase operation. further writes of the resume command ar e ignored. another erase suspend command can be written after the device has resumed erasing.
A29801B series preliminary (june, 2016, version 0.0) 15 amic technology, corp. table 5. A29801B command definitions bus cycles (notes 2 - 4) first second third fourth fifth sixth command sequence (note 1) cycles addr data addr data addr data addr data addr data addr data read (notes 5, 6) 1 ra rd reset (note 6) 1 xxx f0 word 555 2aa 555 manufacturer id byte 4 aaa aa 555 55 aaa 90 x00 37 word 555 2aa 555 x01 22d6 device id, top boot block byte 4 aaa aa 555 55 aaa 90 x02 d6 word 555 2aa 555 x01 2258 device id, bottom boot block byte 4 aaa aa 555 55 aaa 90 x02 58 word 555 2aa 555 x03 continuation id byte 4 aaa aa 555 55 aaa 90 x06 7f xx00 word 555 2aa 555 (sa) x02 xx01 00 autoselect (note 7) sector protect verify (note 8) byte 4 aaa aa 555 55 aaa 90 (sa) x04 01 word 555 2aa 555 program byte 4 aaa aa 555 55 aaa a0 pa pd word 555 2aa 555 unlock bypass byte 3 aaa aa 555 55 aaa 20 unlock bypass program (note 9) 2 xxx a0 pa pd unlock bypass reset (note 10) 2 xxx 90 xxx 00 word 555 2aa 555 555 2aa 555 chip erase byte 6 aaa aa 555 55 aaa 80 aaa aa 555 55 aaa 10 word 555 2aa 555 555 2aa sector erase byte 6 aaa aa 555 55 aaa 80 aaa aa 555 55 sa 30 erase suspend (note 11) 1 xxx b0 erase resume (note 12) 1 xxx 30 legend: x = don't care ra = address of the memory location to be read. rd = data read from location ra during read operation. pa = address of the memory location to be prog rammed. addresses latch on the falling edge of the we or ce pulse, whichever happens later. pd = data to be programmed at location pa. data latches on the rising edge of we or ce pulse, whichever happens first. sa = address of the sector to be verified (in autoselect mode ) or erased. address bits a18 - a12 select a unique sector. note: 1. see table 1 for description of bus operations. 2. all values are in hexadecimal. 3. except when reading array or autoselect data, all bus cycles are write operation. 4. address bits a18 - a11 are don't cares for unlock and command cycles, unless sa or pa required. 5. no unlock or command cycles required when reading array data. 6. the reset command is required to return to reading arra y data when device is in the autoselect mode, or if i/o 5 goes high (while the device is providing status data). 7. the fourth cycle of the autoselec t command sequence is a read cycle. 8. the data is 00h for an unprotec ted sector and 01h for a prot ected sector. see ?autoselec t command sequence? for more information. 9. the unlock bypass command is required prior to the unlock bypass program command. 10. the unlock bypass reset command is required to return to reading array data when the device is in the unlock bypass mode. 11. the system may read and program in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. 12. the erase resume command is valid only during the erase suspend mode.
A29801B series preliminary (june, 2016, version 0.0) 16 amic technology, corp. write operation status several bits, i/o 2 , i/o 3 , i/o 5 , i/o 6 , i/o 7, ry/ by are provided in the A29801B to determine the st atus of a write operation. table 6 and the following subsections describe the functions of these status bits. i/o 7 , i/o 6 and ry/ by each offer a method for determining whether a program or erase operation is complete or in pr ogress. these three bits are discussed first. i/o 7 : data polling the data polling bit, i/o 7 , indicates to the host system whether an embedded algorithm is in progress or completed, or whether the device is in erase suspend. data polling is valid after the rising edge of the final we pulse in the program or erase command sequence. during the embedded program al gorithm, the device outputs on i/o 7 the complement of the datum programmed to i/o 7 . this i/o 7 status also applies to programming during erase suspend. when the embedded program algorithm is complete, the device outputs the datum programmed to i/o 7 . the system must provide the program address to read valid status information on i/o 7 . if a program address falls within a protected sector, data polling on i/o 7 is active for approximately 2 s, then the device returns to reading array data. during the embedded erase algorithm, data polling produces a "0" on i/o 7 . when the embedded erase algorithm is complete, or if the device enters the erase suspend mode, data polling produces a "1" on i/o 7 .this is analogous to the complement/true datum output described for the embedded program algorithm: the erase func tion changes all the bits in a sector to "1"; prior to this, the device outputs the "complement," or "0." the system must provide an address within any of the sectors selected for erasure to read valid status information on i/o 7 . after an erase command sequence is written, if all sectors selected for erasing are protected, data polling on i/o 7 is active for approximately 100 s, then the device returns to reading array data. if not all sele cted sectors are protected, the embedded erase algorith m erases the unprotected sectors, and ignores the selected sectors that are protected. when the system detects i/o 7 has changed from the complement to true data, it can read valid data at i/o 7 - i/o 0 on the following read cycles. this is because i/o 7 may change asynchronously with i/o 0 - i/o 6 while output enable ( oe ) is asserted low. the data polling timings (during embedded algorithms) figure in the "ac characteristics" section illustrates this. table 6 shows the outputs for data polling on i/o 7 . figure 5 shows the data polling algorithm. start read i/o 7 -i/o 0 address = va i/o 7 = data ? fail no note : 1. va = valid address for programming. during a sector erase operation, a valid address is an address within any sector selected for erasure. during chip erase, a valid address is any non-protected sector address. 2. i/o 7 should be rechecked even if i/o 5 = "1" because i/o 7 may change simultaneously with i/o 5 . no read i/o 7 - i/o 0 address = va i/o 5 = 1? i/o 7 = data ? yes no pass yes yes figure 5. data polling algorithm
A29801B series preliminary (june, 2016, version 0.0) 17 amic technology, corp. ry/ by : read/ busy the ry/ by is a dedicated, open-drain output pin that indicates whether an embedded algorithm is in progress or complete. the ry/ by status is valid after the rising edge of the final we pulse in the command sequence. since ry/ by is an open-drain output, several ry/ by pins can be tied together in parallel with a pull-up resistor to vcc. if the output is low (busy), the device is actively erasing or programming. (this includes programming in the erase suspend mode.) if the output is high (ready), the device is ready to read array data (inc luding during the erase suspend mode), or is in the standby mode. table 6 shows the outputs for ry/ by . refer to ? reset timings?, ?timing waveforms for program operation? and ?timing waveforms for chip/sector erase operation? for more information. i/o 6 : toggle bit i toggle bit i on i/o 6 indicates whether an embedded program or erase algorithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address, and is valid after the rising edge of the final we pulse in the command sequence (prior to the program or erase operation) , and during the sector erase time-out. during an embedded program or erase algorithm operation, successive read cycles to any address cause i/o 6 to toggle. (the system may use either oe or ce to control the read cycles.) when the operation is complete, i/o 6 stops toggling. after an erase command sequence is written, if all sectors selected for erasing are protected, i/o 6 toggles for approximately 100 s, then returns to reading array data. if not all selected sectors are pr otected, the embedded erase algorithm erases the unprotec ted sectors, and ignores the selected sectors that are protected. the system can use i/o 6 and i/o 2 together to determine whether a sector is actively erasing or is erase-suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), i/o 6 toggles. when the device enters the erase suspend mode, i/o 6 stops toggling. however, the system must also use i/o 2 to determine which sectors are erasing or erase- suspended. alternatively, the system can use i/o 7 (see the subsection on " i/o 7 : data polling"). if a program address falls within a protected sector, i/o 6 toggles for approximately 2 s after the program command sequence is written, then returns to reading array data. i/o 6 also toggles during the erase-suspend-program mode, and stops toggling once the embedded program algorithm is complete. the write operation status table shows the outputs for toggle bit i on i/o 6 . refer to figure 6 for the toggle bit algorithm, and to the toggle bit timings figure in the "ac characteristics" section for the timing diagram. the i/o 2 vs. i/o 6 figure shows the differences between i/o 2 and i/o 6 in graphical form. see also the subsection on " i/o 2 : toggle bit ii". i/o 2 : toggle bit ii the "toggle bit ii" on i/o 2 , when used with i/o 6 , indicates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we pulse in the command sequence. i/o 2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (the system may use either oe or ce to control the read cycles.) but i/o 2 cannot distinguish whether the sect or is actively erasing or is erase-suspended. i/o 6 , by comparison, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are selected for erasure. thus, both status bits are required fo r sector and mode information. refer to table 6 to compare outputs for i/o 2 and i/o 6 . figure 6 shows the toggle bit algor ithm in flowchart form, and the section " i/o 2 : toggle bit ii" explains the algorithm. see also the " i/o 6 : toggle bit i" subsection. refer to the toggle bit timings figure for the togg le bit timing diagram. the i/o 2 vs. i/o 6 figure shows the differences between i/o 2 and i/o 6 in graphical form. reading toggle bits i/o 6 , i/o 2 refer to figure 6 for the following discussion. whenever the system initially begins reading toggle bit status, it must read i/o 7 - i/o 0 at least twice in a row to determine whether a toggle bit is toggling. typically, a system would note and store the value of the toggle bit after the first read. after the second read, the system would compar e the new value of the toggle bit with the first. if the toggle bi t is not toggling, the device has completed the program or eras e operation. the system can read array data on i/o 7 - i/o 0 on the following read cycle. however, if after the initia l two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of i/o 5 is high (see the section on i/o 5 ). if it is, the system should then determine again whether the toggle bit is togg ling, since the toggle bit may have stopped toggling just as i/o 5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. if it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially determines that the toggle bit is toggling and i/o 5 has not gone high. the system may continue to monitor the toggle bit and i/o 5 through successive read cycles, determining the status as described in the previous paragr aph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of figure 6). i/o 5 : exceeded timing limits i/o 5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. under these conditions i/o 5 produces a "1." this is a failure condition that indicates the program or erase cycle was not successfully completed.
A29801B series preliminary (june, 2016, version 0.0) 18 amic technology, corp. the i/o 5 failure condition may appear if the system tries to program a "1 "to a location that is previously programmed to "0." only an erase operation can change a "0" back to a "1." under this condition, the device halts the operation, and when the operation has exceeded the timing limits, i/o 5 produces a "1." under both these conditions, the system must issue the reset command to return the device to reading array data. i/o 3 : sector erase timer after writing a sector erase command sequence, the system may read i/o 3 to determine whether or not an erase operation has begun. (the sector erase timer does not apply to the chip erase command.) if additional sectors are selected for erasure, the entir e time-out also applies after each additional sector erase co mmand. when the time-out is complete, i/o 3 switches from "0" to "1." the system may ignore i/o 3 if the system can guar antee that the time between additional sector erase commands will always be less than 50 s. see also the "sector erase command sequence" section. after the sector erase command sequence is written, the system should read the status on i/o 7 ( data polling) or i/o 6 (toggle bit 1) to ensure the device has accepted the command sequence, and then read i/o 3 . if i/o 3 is "1", the internally controlled erase cycle has begun; all further commands (other than erase su spend) are ignored until the erase operation is complete. if i/o 3 is "0", the device will accept additional sector erase commands. to ensure the command has been accepted, the system software should check the status of i/o 3 prior to and following each subsequent sector erase command. if i/o 3 is high on the second status check, the la st command might not have been accepted. table 6 shows the outputs for i/o 3 . start read i/o 7 -i/o 0 toggle bit = toggle ? program/erase operation not commplete, write reset command yes notes : 1. read toggle bit twice to determine whether or not it is toggling. see text. 2. recheck toggle bit because it may stop toggling as i/o 5 changes to "1". see text. no read i/o 7 - i/o 0 twice i/o 5 = 1? toggle bit = toggle ? yes yes program/erase operation complete no no read i/o 7 -i/o 0 (notes 1,2) figure 6. toggle bit algorithm (note 1)
A29801B series preliminary (june, 2016, version 0.0) 19 amic technology, corp. table 6. write operation status i/o 7 i/o 6 i/o 5 i/o 3 i/o 2 ry/ by operation (note 1) (note 2) (note 1) embedded program algorithm 7 i/o toggle 0 n/a no toggle 0 standard mode embedded erase algorithm 0 toggle 0 1 toggle 0 reading within erase suspended sector 1 no toggle 0 n/a toggle 1 reading within non-erase suspend sector data data data data data 1 erase suspend mode erase-suspend-program 7 i/o toggle 0 n/a n/a 0 notes: 1. i/o 7 and i/o 2 require a valid address when reading status information. refer to the appropriate subsection for further details. 2. i/o 5 switches to ?1? when an embedded program or embedded erase operation has exceeded the maximum timing limits. see ?i/o5: exceeded timing limits? for more information. maximum negative input overshoot 20ns 20ns 20ns +0.8v -0.5v -2.0v maximum positive input overshoot 20ns 20ns 20ns vcc+0.5v 2.0v vcc+2.0v
A29801B series preliminary (june, 2016, version 0.0) 20 amic technology, corp. dc characteristics cmos compatible parameter symbol parameter description test description min. typ. max. unit i li input leakage current v in = vss to vcc. vcc = vcc max 2.0 a i lit a9 input load current vcc = v cc max, a9 =11.5v 35 a i lo output leakage current v out = vss to vcc. vcc = vcc max 2.0 a 5 mhz 8 40 ce = v il , oe = v ih byte mode 1 mhz 1.6 8 5 mhz 12 50 i cc1 vcc active read current (notes 1, 2) ce = v il , oe = v ih word mode 1 mhz 2.4 12 ma i cc2 vcc active write (program/erase) current (notes 2, 3, 4) ce = v il , oe =v ih 30 50 ma i cc3 vcc standby current (note 2) ce = v ih , reset = vcc 0.5v 6 150 ua i cc4 vcc standby current during reset (note 2) reset = vss 0.5v 6 150 a v il input low level -0.5 0.8 v v ih input high level 3.3 vcc + 0.5 v v id voltage for autoselect and temporary unprotect sector vcc = 5.0 v 9.5 10.5 11.5 v v ol output low voltage i ol = 6.0ma, vcc = vcc min 0.45 v v oh1 i oh = -2.5 ma, vcc = vcc min 0.8 x vcc v v oh2 output high voltage i oh = -100 a, vcc = vcc min vcc - 0.4 v v lko low vcc lockout voltage (n ote 4) 3.1 3.6 4.1 v notes: 1. the i cc current listed is typically less than 2 ma/mhz, with oe at v ih . typical vcc is 5.0v. 2. maximum i cc specifications are tested with vcc = vcc max. 3. i cc active while embedded algorithm (program or erase) is in progress. 4. not 100% tested.
A29801B series preliminary (june, 2016, version 0.0) 21 amic technology, corp. dc characteristics (continued) typical word mode active read current, t=25c 0.0 5.0 10.0 15.0 20.0 25.0 30.0 2345678910 frequency in mhz power supply current in ma 4.5v 5.0v 5.5v
A29801B series preliminary (june, 2016, version 0.0) 22 amic technology, corp. ac characteristics read only operations parameter symbols speed jedec std description test setup -55 unit t avav t rc read cycle time (note 1) min. 55 ns t avqv t acc address to output delay ce = v il oe = v il max. 55 ns t elqv t ce chip enable to output delay oe = v il max. 55 ns t glqv t oe output enable to output delay max. 25 ns read min. 0 ns t oeh output enable hold time (note 1) toggle and data polling min. 10 ns t ehqz t df chip disable to output high z (notes 1) max. 20 ns t ghqz t df output disable to output high z (notes 1) max. 20 ns t axqx t oh output hold time from addresses, ce or oe , whichever occurs first (note 1) min. 0 ns notes: 1. not 100% tested. 2. see test conditions and test setup for test specifications. timing waveforms for read only operation addresses addresses stable ce oe we output valid high-z output t rc t oeh t oe t ce high-z t oh t df t acc 0v reset ry/by
A29801B series preliminary (june, 2016, version 0.0) 23 amic technology, corp. ac characteristics hardware reset ( reset ) parameter jedec std description test setup all speed options unit t ready reset pin low (during embedded algorithms) to read or write (see note) max 20 s t ready reset pin low (not during embedded algorithms) to read or write (see note) max 500 ns t rp reset pulse width min 500 ns t rh reset high time before read (see note) min 50 ns t rb ry/ by recovery time min 0 ns t rpd reset low to standby mode min 20 s note: not 100% tested. reset timings ce, oe reset t rh t rp t ready reset timings not during embedded algorithms reset t rp ~ ~ reset timings during embedded algorithms ry/by ~ ~ t rb ~ ~ t ready ce, oe ry/by
A29801B series preliminary (june, 2016, version 0.0) 24 amic technology, corp. temporary sector unprotect parameter jedec std description all speed options unit t vidr v id rise and fall time (see note) min 500 ns t rsp reset setup time for temporary sector unprotect min 4 s note: not 100% tested. temporary sector unprotect timing diagram ac characteristics word/byte configuration ( byte ) parameter jedec std description all speed options unit t elfl/ t elfh ce to byte switching low or high max 5 ns t flqz byte switching low to output high-z max 25 ns t hqv byte switching high to output active min 55 ns program or erase command sequence reset ~ ~ ~ ~ ~ ~ 10.5v 0 or 5v t vidr t vidr 0 or 5v t rsp ce we ry/by ~ ~
A29801B series preliminary (june, 2016, version 0.0) 25 amic technology, corp. data output (i/o 0 -i/o 14 ) data output (i/o 0 -i/o 7 ) i/o 15 output address input data output (i/o 0 -i/o 14 ) data output (i/o 0 -i/o 7 ) i/o 15 output address input t fhqv t flqz t elfh t elfl ce oe byte i/o 0 -i/o 14 i/o 15 (a-1) byte i/o 0 -i/o 14 i/o 15 (a-1) byte switching from word to byte mode byte switching from byte to word mode byte timings for read operations byte timings for write operations note: refer to the erase/program operations table for t as and t ah specifications. the falling edge of the last we signal t hold (t ah ) t set (t as ) ce byte we
A29801B series preliminary (june, 2016, version 0.0) 26 amic technology, corp. ac characteristics erase and program operations parameter speed jedec std description -55 unit t avav t wc write cycle time (note 1) min. 55 ns t avwl t as address setup time min. 0 ns t wlax t ah address hold time min. 40 ns t dvwh t ds data setup time min. 30 ns t whdx t dh data hold time min. 0 ns t oes output enable setup time min. 0 ns t ghwl t ghwl read recover time before write ( oe high to we low) min. 0 ns t elwl t cs ce setup time min. 0 ns t wheh t ch ce hold time min. 0 ns t wlwh t wp write pulse width min. 35 ns t whwl t wph write pulse width high min. 20 ns byte typ. 6 t whwh1 t whwh1 byte programming operation (note 2) word typ. 11 s t whwh2 t whwh2 sector erase operation (note 2) typ. 0.3 sec t vcs vcc set up time (note 1) min. 50 s t rb recovery time from ry/ by min 0 ns t busy program/erase valid to ry/ by delay min 30 ns notes: 1. not 100% tested. 2. see the "erase and programming perfo rmance" section for more information.
A29801B series preliminary (june, 2016, version 0.0) 27 amic technology, corp. timing waveforms for program operation addresses ce oe we data vcc a0h pd t wc pa program command sequence (last two cycles) pa d out ~ ~ ~ ~ pa ~ ~ status ~ ~ ~ ~ ~ ~ ~ ~ t as t vcs read status data (last two cycles) 555h t ah t whwh1 t ch t wp t wph t cs t ds t dh note : 1. pa = program addrss, pd = program data, dout is the true data at the program address. 2. illustration shows device in word mode. ~ ~ t rb t busy ry/by
A29801B series preliminary (june, 2016, version 0.0) 28 amic technology, corp. addresses ce oe we data vcc 55h 30h t wc sa erase command sequence (last two cycles) va complete ~ ~ ~ ~ va ~ ~ in progress ~ ~ ~ ~ ~ ~ ~ ~ t as t vcs read status data 2aah t ah t whwh2 t ch t wp t wph t cs t ds t dh note : 1. sa = sector address (for sector erase), va = valid address for reading status data (see "write operaion ststus"). 2. illustratin shows device in word mode. 555h for chip erase 10h for chip erase ~ ~ t rb t busy ry/by timing waveforms for chip/sector erase operation
A29801B series preliminary (june, 2016, version 0.0) 29 amic technology, corp. timing waveforms for data polling (during embedded algorithms) addresses ce oe we i/o 7 t rc va va va ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ complement ~ ~ complement true valid data high-z status data ~ ~ status data true valid data high-z i/o 0 - i/o 6 t acc t ce t ch t oe t oeh t df t oh note : va = valid address. illustation shows first status cycle after command sequence, last status read cycle, and array data read cycle. ~ ~ t busy ry/by high-z
A29801B series preliminary (june, 2016, version 0.0) 30 amic technology, corp. timing waveforms for toggle bit (during embedded algorithms) note: va = valid address; not required for i/o 6 . illustration shows first two status cy cle after command sequence, last status read cycle, and array data read cycle. addresses ce oe we i/o 6 , i/o 2 t rc va va va ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ valid status t acc t ce t ch t oe t oeh t df t oh va valid status valid status valid data ~ ~ (first read) (second read) (stop togging) ry/by ~ ~ t busy high-z
A29801B series preliminary (june, 2016, version 0.0) 31 amic technology, corp. timing waveforms for sector protect/unprotect v id note : for sector protect, a6=0, a1=1, a0=0. for sector unprotect, a6=1, a1=1, a0=0 ~ ~ ~ ~ ~ ~ ~ ~ v ih reset sa, a6, a1, a0 data ce we oe valid* valid* valid* 60h 60h 40h status sector protect/unprotect verify 1us sector protect:150us sector unprotect:15ms timing waveforms for i/o 2 vs. i/o 6 enter embedded erasing erase suspend enter erase suspend program erase resume we i/o 6 i/o 2 erase erase suspend read erase suspend read erase erase complete i/o 2 and i/o 6 toggle with oe and ce note : both i/o 6 and i/o 2 toggle with oe or ce. see the text on i/o 6 and i/o 2 in the section "write operation status" for more information. ~ ~ ~ ~ ~ ~ erase suspend program ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
A29801B series preliminary (june, 2016, version 0.0) 32 amic technology, corp. ac characteristics erase and program operations alternate ce controlled writes parameter speed jedec std description -55 unit t avav t wc write cycle time (note 1) min. 55 ns t avel t as address setup time min. 0 ns t elax t ah address hold time min. 40 ns t dveh t ds data setup time min. 30 ns t ehdx t dh data hold time min. 0 ns t oes output enable setup time min. 0 ns t ghel t ghel read recover time before write ( oe high to we low) min. 0 ns t wlel t ws we setup time min. 0 ns t ehwh t wh we hold time min. 0 ns t eleh t cp ce pulse width min. 35 ns t ehel t cph ce pulse width high min. 20 ns byte typ. 6 t whwh1 t whwh1 programming operation (note 2) word typ. 11 s t whwh2 t whwh2 sector erase operation (note 2) typ. 0.3 sec notes: 1. not 100% tested. 2. see the "erase and programming perfo rmance" section for more information.
A29801B series preliminary (june, 2016, version 0.0) 33 amic technology, corp. timing waveforms for alternate ce controlled write operation addresses we oe ce data 555 for program 2aa for erase pa d out ~ ~ ~ ~ i/o 7 ~ ~ ~ ~ ~ ~ data polling note : 1. pa = program address, pd = program data, sa = sector address, i/o 7 = complement of data input, d out = array data. 2. figure indicates the last two bus cycles of the command sequence. pd for program 30 for sector erase 10 for chip erase ~ ~ t busy t whwh1 or 2 t ah t as t wc t wh t cp t ws t cph pa for program sa for sector erase 555 for chip erase a0 for program 55 for erase t rh t ds t dh ~ ~ ~ ~ reset ry/by erase and programming performance parameter typ. (note 1) max. (note 2) unit comments sector erase time 0.3 1.5 sec chip erase time 4 16 sec excludes 00h programming prior to erasure byte programming time 6 100 s word programming time 11 180 s byte mode 4 16 sec chip programming time (note 3) word mode 3 12 sec excludes system-level overhead (note 5) notes: 1. typical program and erase times assume the following conditions: 25 c, 5.0v vcc, 10,000 cycles. additionally, programming typically assumes checkerboard pattern. 2. under worst case conditions of 90 c, vcc = 4.5v, 100,000 cycles. 3. the typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum byte program time listed. if t he maximum byte program time given is exceeded, only then does the device set i/o 5 = 1. see the section on i/o 5 for further information. 4. in the pre-programming step of the embedded erase algorithm, all bytes are programmed to 00h before erasure. 5. system-level overhead is the time required to execute the four-bus-cycle command sequence for programming. see table 5 for further information on command definitions. 6. the device has a guaranteed minimum erase an d program cycle endurance of 100,000 cycles.
A29801B series preliminary (june, 2016, version 0.0) 34 amic technology, corp. latch-up characteristics description min. max. input voltage with respect to vss on all i/o pins -1.0v vcc+1.0v vcc current -100 ma +100 ma input voltage with respect to vss on all pins except i/o pins (including a9, oe and reset ) -1.0v 11.5v includes all pins except vcc. test conditions: vcc = 5.0v, one pin at time. tsop pin capacitance parameter symbol parameter description test setup typ. max. unit c in input capacitance v in =0 6 7.5 pf c out output capacitance v out =0 8.5 12 pf c in2 control pin capacitance v in =0 7.5 9 pf notes: 1. sampled, not 100% tested. 2. test conditions t a = 25 c, f = 1.0mhz
A29801B series preliminary (june, 2016, version 0.0) 35 amic technology, corp. test conditions test specifications test condition -55 unit output load 1 ttl gate output load capacitance, c l (including jig capacitance) 30 pf input rise and fall times 5 ns input pulse levels 0.0 - 3.0 v input timing measurement reference levels 1.5 v output timing measurement reference levels 1.5 v test setup 6.2 k device under test c l diodes = in3064 or equivalent 2.7 k 5.0 v ? ?
A29801B series preliminary (june, 2016, version 0.0) 36 amic technology, corp. part numbering scheme a29 x package type v = 48-pin tsop g = 48-ball bga device version* b = b chip version device type a29 = amic 5v single bank parallel nor flash device density 400 = 4mbits 800 = 8mbits 801 = 8mbits 160 = 16mbits temperature* x package material f = pb free x * optional x xxx / x packing q = tape & reel x t = top boot u = bottom boot xx speed grade c 85 ~ c 40 - u + = c 70 ~ c 0 blank + =
A29801B series preliminary (june, 2016, version 0.0) 37 amic technology, corp. ordering information top boot sector flash part no. access time (ns) active read current typ. (ma) program/erase current typ. (ma) standby current typ. ( a ) package A29801Btv-55f 48 pin pb-free tsop A29801Btv-55uf 48 pin pb-free tsop A29801Btg-55f 48 ball pb-free tfbga A29801Btg-55uf 55 20 30 0.5 48 ball pb-free tfbga -u is for industrial operating temperature range: -40 c to +85 c. bottom boot sector flash part no. access time (ns) active read current typ. (ma) program/erase current typ. (ma) standby current typ. ( a ) package A29801Buv-55f 48 pin pb-free tsop A29801Buv-55uf 48 pin pb-free tsop A29801Bug-55f 48 ball pb-free tfbga A29801Bug-55uf 55 20 30 0.5 48 ball pb-free tfbga -u is for industrial operating temperature range: -40 c to +85 c.
A29801B series preliminary (june, 2016, version 0.0) 38 amic technology, corp. package information tsop 48l (type i) outline dimensions unit: inches/mm 1 e c d l detail "a" 0.25 24 25 48 d 1 d y e s a 1 a 2 a detail "a" b dimensions in inches dimensions in mm symbol min nom max min nom max a - - 0.047 - - 1.20 a 1 0.002 - 0.006 0.05 - 0.15 a 2 0.037 0.039 0.042 0.94 1.00 1.06 b 0.007 0.009 0.011 0.18 0.22 0.27 c 0.004 - 0.008 0.12 - 0.20 d 0.779 0.787 0.795 19.80 20.00 20.20 d 1 0.720 0.724 0.728 18.30 18.40 18.50 e - 0.472 0.476 - 12.00 12.10 e 0.020 basic 0.50 basic l 0.020 0.024 0.0275 0.50 0.60 0.70 s 0.011 typ. 0.28 typ. y - - 0.004 - - 0.10 0 - 8 0 - 8 notes: 1. the maximum value of dimension d includes end flash. 2. dimension e does not include resin fins. 3. dimension s includes end flash.
A29801B series preliminary (june, 2016, version 0.0) 39 amic technology, corp. package information 48 balls csp (6 x 8 mm) outline dimensions unit: mm (48tfbga) a 1 h g f e d c b a top view side view c seating plane 654321 bottom view ball*a1 corner h g f e d c b a e e 1 e e d 1 d b 0.10 c a 123456 dimensions in mm symbol min. nom. max. a - - 1.20 a 1 0.20 0.25 0.30 b 0.30 - 0.40 d 5.90 6.00 6.10 d 1 4.00 bsc e - 0.80 - e 7.90 8.00 8.10 e 1 5.60 bsc

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